1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and relates particularly to a semiconductor integrated circuit device operating in a burst mode and comprising an internal power supply circuit for converting a power supply voltage from an external system to a particular voltage and supplying the converted voltage to the internal circuits of the semiconductor integrated circuit device.
2. Description of the Prior Art
FIG. 15 is a block diagram of an 64 Mbit.times.8 synchronous DRAM device operating in a burst mode according to the prior art.
As shown in FIG. 15, the synchronous DRAM (SDRAM below) 200 device comprises an internal power supply circuit 205, address buffer 206, control signal buffer 207, clock buffer 208, four memory array banks 209, 210, 211, and 212, input/output (I/O) buffer 213 for data input and output, mode register 214, and a control circuit 215 for controlling the memory array banks 209-212 and I/O buffer 213. The internal power supply circuit 205 comprises an internal voltage step-down circuit 201, substrate voltage generator 202, step-up voltage generator 203, and reference voltage generator 204.
The internal voltage step-down circuit 201 drops the power supply voltage supplied from an external system to power supply terminal Vcc to produce an internal power supply voltage int.Vcc to be supplied to the internal circuits of the SDRAM 200. The value of internal power supply voltage int.Vcc is determined according to the reference voltage Vref input from the reference voltage generator 204. More specifically, the internal voltage step-down circuit 201 controls and outputs the internal power supply voltage int.Vcc at the level of the reference voltage Vref supplied from the reference voltage generator 204.
The substrate voltage generator 202 generates and outputs a bias voltage of a semiconductor substrate of the device, and applies a negative substrate voltage Vbb to the semiconductor substrate.
The step-up voltage generator 203 steps up the power supply voltage from the power supply terminal Vcc to generate and supply step-up voltage Vpp to each of the memory array banks 209-212.
The address buffer 206 is connected to the address signal input terminals to which address signals are input from an external system. These input terminals may include, for example, bank address terminals BA0 and BA1 from which the bank address selection signals are input, and the address terminals A0-A11 through which the address signals are input.
The control signal buffer 207 is connected to each of the control signal input terminals through which the control signals are input from the external system. These control signal input terminals include in this example the /CS terminal to which a chip selector signal is input, the /RAS terminal to which a row address strobe signal is input, the /CAS terminal to which a column address strobe signal is input, the /WE terminal to which a write enable signal is input, and the DQM terminal to which an I/O mask signal is input.
The clock buffer 208 generates the internal clock signal from an externally supplied clock signal, and supplies the clock signal to the connected address buffer 206, control signal buffer 207, I/O buffer 213, and control circuit 215. The external clock signal is supplied to the clock buffer 208 through the CLK terminal, and a clock enable signal is supplied to the clock buffer 208 through the CKE terminal.
The control circuit 215 is connected to each of the memory array banks 209-212, the address buffer 206, the control signal buffer 207, and the I/O buffer 213. The mode register 214 is used by the control circuit 215 when determining the burst length from the address signals input from the address signal input terminals.
A typical SDRAM 200 thus comprised can change the burst length to 1, 2, 4, or 8 bits. When, for example, the /CS terminal, /RAS terminal, /CAS terminal, and /WE terminal are all LOW, the control circuit 215 outputs a set signal to the mode register 214, thereby causing the mode register 214 to latch the particular plural address signals input from the address buffer 206 indicating the burst length. The control circuit 215 then references the signal levels latched by the mode register 214 to control the burst length used for burst transfers.
Current consumption is greater when the burst length is long than when the burst length is short, and the drop in the internal power supply voltage int.Vcc and step-up voltage Vpp output from the internal voltage step-down circuit 201 and step-up voltage generator 203 thus increases. In addition, the negative substrate voltage Vbb output from the substrate voltage generator 202 tends to be higher when the burst length is long than when the burst length is short.